GPUDatacenterReleased May 14, 2020

NVIDIA A100 SXM4 40GB

40 GB HBM2 · 5120-bit · 6,912 cores

The original SXM4 module version of NVIDIA's Ampere data center accelerator, built for HGX and DGX A100 systems in which eight GPUs are linked over NVLink and NVSwitch. Ampere introduced TF32 Tensor Core math, structured sparsity and Multi-Instance GPU partitioning. It has no display outputs, RT Cores or video encoder.

General

Manufacturer: NVIDIA
Model: A100 SXM4 40GB
Segment: Datacenter
GPU chip: GA100
Architecture: Ampere
Release date: May 14, 2020
Price: Search on Amazon

Memory

Memory size: 40 GB
Memory type: HBM2
Bus width: 5120-bit
Bandwidth: 1,555 GB/s
Memory clock: 1,215 MHz

Clocks & silicon

GPU clock: —
Boost clock: 1,410 MHz
Shader units: 6,912 CUDA Cores
Tensor / AI cores: 432
RT cores: —
Transistors: 54.2 billion
Technology (nm): 7 nm
TSMC N7
TDP / TBP: 400 W

Interface & APIs

Bus interface: SXM4 (PCIe 4.0 x16 host)
SLI / multi-GPU: NVLink 3.0 (600 GB/s)
DirectX: N/A (compute-only)
OpenGL: N/A (compute-only)
Vulkan: N/A (compute-only)
Other APIs: CUDA (compute capability 8.0)

AI support

Precisions: FP8FP16BF16INT8INT4TF32FP64
AI accelerator: Third-generation Tensor Cores (432)
Peak AI TOPS: 1,248 TOPS
Notes: Third-generation Tensor Cores supporting FP64, TF32, BF16, FP16, INT8, INT4 and binary; FP8 arrived with Hopper. Peak throughput with structured sparsity: INT8 1,248 TOPS, FP16 and BFLOAT16 624 TFLOPS, TF32 312 TFLOPS; dense rates are half. FP64 is 9.7 TFLOPS, FP64 Tensor Core and FP32 19.5 TFLOPS each. Multi-Instance GPU partitions the card into up to seven instances.

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